// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  mdma_reg_offset_field.h
// Project line  :  K3
// Department    :  K3
// Author        :  Huawei
// Version       :  V100
// Date          :  2015/4/10
// Description   :  HiVcodecV100 VDEC
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/04/10 10:02:42 Create file
// ******************************************************************************

#ifndef __MDMA_REG_OFFSET_FIELD_H__
#define __MDMA_REG_OFFSET_FIELD_H__

#define MDMA_SRC_LUMA_BASE_ADDR_LEN    32
#define MDMA_SRC_LUMA_BASE_ADDR_OFFSET 0

#define MDMA_SRC_CHMA_BASE_ADDR_LEN    32
#define MDMA_SRC_CHMA_BASE_ADDR_OFFSET 0

#define MDMA_DST_LUMA_BASE_ADDR_LEN    32
#define MDMA_DST_LUMA_BASE_ADDR_OFFSET 0

#define MDMA_DST_CHMA_BASE_ADDR_LEN    32
#define MDMA_DST_CHMA_BASE_ADDR_OFFSET 0

#define MDMA_IMG_HEIGHT_IN_PIX_LEN    14
#define MDMA_IMG_HEIGHT_IN_PIX_OFFSET 18
#define MDMA_NCMP_DATA_STRIDE_LEN     18
#define MDMA_NCMP_DATA_STRIDE_OFFSET  0

#define MDMA_HEAD_STRIDE_LEN    14
#define MDMA_HEAD_STRIDE_OFFSET 18
#define MDMA_UVSTRIDE_LEN       18
#define MDMA_UVSTRIDE_OFFSET    0

#define MDMA_IMG_HEIGHT_IN_MB_LEN    9
#define MDMA_IMG_HEIGHT_IN_MB_OFFSET 16
#define MDMA_IMG_WIDTH_IN_MB_LEN     9
#define MDMA_IMG_WIDTH_IN_MB_OFFSET  0

#define MDMA_DDR_INTERLEAVE_MODE_LEN    2
#define MDMA_DDR_INTERLEAVE_MODE_OFFSET 26
#define MDMA_DST_STORE_MODE_LEN         2
#define MDMA_DST_STORE_MODE_OFFSET      24
#define MDMA_SRC_LODE_MODE_LEN          2
#define MDMA_SRC_LODE_MODE_OFFSET       22
#define MDMA_BITDEPTH_LEN               4
#define MDMA_BITDEPTH_OFFSET            18
#define MDMA_TILE_LINEAR_MODE_LEN       1
#define MDMA_TILE_LINEAR_MODE_OFFSET    17
#define MDMA_FRM_CMP_EN_LEN             1
#define MDMA_FRM_CMP_EN_OFFSET          16
#define MDMA_DMA_CMD_NUM_MIN1_LEN       16
#define MDMA_DMA_CMD_NUM_MIN1_OFFSET    0

#define MDMA_IN_START_MBY_LEN    9
#define MDMA_IN_START_MBY_OFFSET 16
#define MDMA_IN_START_MBX_LEN    9
#define MDMA_IN_START_MBX_OFFSET 0

#define MDMA_IN_END_MBY_LEN    9
#define MDMA_IN_END_MBY_OFFSET 16
#define MDMA_IN_END_MBX_LEN    9
#define MDMA_IN_END_MBX_OFFSET 0

#define MDMA_IN_MBY_LEN    9
#define MDMA_IN_MBY_OFFSET 16
#define MDMA_IN_MBX_LEN    9
#define MDMA_IN_MBX_OFFSET 0

#define MDMA_SEND_MBY_LEN    9
#define MDMA_SEND_MBY_OFFSET 16
#define MDMA_SEND_MBX_LEN    9
#define MDMA_SEND_MBX_OFFSET 0

#define MDMA_DMA_CMD_CNT_LEN    16
#define MDMA_DMA_CMD_CNT_OFFSET 16
#define MDMA_CUR_EMAR_ST_LEN    2
#define MDMA_CUR_EMAR_ST_OFFSET 8
#define MDMA_CUR_SEND_ST_LEN    3
#define MDMA_CUR_SEND_ST_OFFSET 4
#define MDMA_CUR_ST_DMA_LEN     4
#define MDMA_CUR_ST_DMA_OFFSET  0

#define MDMA_DMA_IN_CNT_LEN      4
#define MDMA_DMA_IN_CNT_OFFSET   16
#define MDMA_CMP_DAT_CNT_LEN     6
#define MDMA_CMP_DAT_CNT_OFFSET  8
#define MDMA_HEAD_INF_CNT_LEN    8
#define MDMA_HEAD_INF_CNT_OFFSET 0

#define MDMA_WEMAR_DATA_CNT_LEN    6
#define MDMA_WEMAR_DATA_CNT_OFFSET 26
#define MDMA_SDAT_CNT_LEN          4
#define MDMA_SDAT_CNT_OFFSET       22
#define MDMA_SEND_INMB_CNT_LEN     6
#define MDMA_SEND_INMB_CNT_OFFSET  16
#define MDMA_SEND_PART_CNT_LEN     16
#define MDMA_SEND_PART_CNT_OFFSET  0

#define MDMA_SRC_HEAD_YSTADDR_LEN    32
#define MDMA_SRC_HEAD_YSTADDR_OFFSET 0

#define MDMA_SRC_HEAD_CSTADDR_LEN    32
#define MDMA_SRC_HEAD_CSTADDR_OFFSET 0

#define MDMA_DST_HEAD_YSTADDR_LEN    32
#define MDMA_DST_HEAD_YSTADDR_OFFSET 0

#define MDMA_DST_HEAD_CSTADDR_LEN    32
#define MDMA_DST_HEAD_CSTADDR_OFFSET 0

#endif // __MDMA_REG_OFFSET_FIELD_H__
